[SOUND] Hello,
everyone.
Welcome back to the Heterogeneous Parallel Programming class.
This is lecture 1.3, Portability and
Scalability in Heterogeneous parallel port, computing.
The objective of this lecture is to help you to understand
the importance and nature of scalability and portability in parallel programming.
This slide shows the data that was published by IBM
in 2010. And this graph shows that the hardware
costs, and software costs have been both growing exponentially
over the years. And this is a log plot, so a linear curve
in this plot is a exponential curve. And the
software cost is measured by lines per chip.
And it has been growing by two times every ten months.
And the hardware cost is measured by gates per chip.
And this is meas- has been increasing by two times every 18 months.
But therefore, the software cost has been
growing much faster than the hardware cost.
So even though
the software cost started to be lower than hardware, but at this point in after
2010 the software cost has essentially exceeded the
hardware cost and it has been growing faster.
So the software cost is going to be much,
much more than hardware costs in the years to come.
So in the future, all the system need to be able
to minimize software development cost or redevelopment cost and
this leads to the consideration of scalability and, and portability.
The first aspect of software cost control is scalability.
If we develop an application to run well on Core A,
what we would like to do is, we would like to make
sure that that same application without significant re-, redevelopment
can run efficiently on the next version of Core A, let's say Core A 2.0.
So this allows us to to use
the same application when a new generation of hardware is introduced.
And when, when, whenever scalability holds then the
developer does not need to re-revise the hard-, the
software in order to run well on the
new generation of software, therefore reducing the redevelopment cost.
There is another dimension of Scalability.
Whenever an application runs well on one Core A, we will also like it to
to run well on multiples of these Core As or more of a same cores.
And this allows us to to, to add
performance by adding more hardware into the system.
Many in many situations, the vendors would like to introduce
multiple versions of hardware and each version will have
increasingly more amount of hardware available to the users.
So if we could develop a piece of software that is
scalable of to run well on more of the same cores,
then this gives the vendor the the scalability of their hardware,
so that when they introduce more hardware the users can actually observe
increased performance from the application.
In the future, we expect that there will be several generations of hardware
where performance will be increased by adjusting many of these parameters.
For example, the number of compute units or
the number of cores, and the number of threads,
the number of the increasing vector length, the
increased increased pipeline depth, and increased DRAM burst size,
increased number of DRAM channels, and increasing data movement latency.
All these hardware parameters will can significantly affect the
performance of the application, and oftentimes applications need to be able
to to be tuned, choose some settings of these parameters.
So, but the programming
style that we use in this le-, course addresses these needs by supporting
fine-grained problem decomposition and dynamic thrust scheduling.
So that the application that you write, according
to this programming style, will be able to
automatically adjust to a fairly wide range of
parameter values that the hardware venders may change.
So this allows your application to to run well on one generation
of hardware and continue to run well on a future generation of hardware.
And also if your application runs well on one of, of the cores, you
can expect the application to also run well on more of the same cores.
The second dimension of software cost control is portability.
Portability is defined as if we develop an application to run well on
core A, we would also like it to be able to run well on different types of cores.
In this case, core B and core C in the picture.
So oftentimes,
the application developed for core A may
be initially running on one vendor product.
And but if the application is portable then the users can expect to run the
same application on different hardware types, oftentimes
from different hardware vendors to also run well.
So these,
this can also decrease the software cost because the
developer will not need to redevelop or revise their application so
that the application can run well on other types of vendors systems.
And a lot of times we will see different design styles from
different vendors. For GPUs, oftentimes we will see very
significant design styles, as illustrated in this picture.
And in, in terms of the particular kinds of differences,
we can expect to see that for the CPU cores we can, we would
see different instructions and architecture such as X86 versus
ARM versus other types of instructions set architectures.
And these iinstructions and architectures oftentimes would
required different compiler co-generation and so on.
So and that, that oftentimes it
will affect the portability of your application.
And we also have different design styles even based on
the same instructions and architecture, we could have Latency oriented CPU
designs versus throughput oriented GPU designs.
And so when we develop a a piece of code,
can we expect to run we, can we expect it to run well on a
latency-oriented CPU if it runs well on a
through-put oriented GPU? And the third kind of dimension
of portability often comes with different
styles of parallelism in the processor core.
There's a design style called VRW and there is
a design style SIMD and there's a design style multi-threading.
So we're going to actually touch quite a bit on this level
of differences for hardware. And then it also will come
to how we organize DRAMs in the system, whether
it's a shared memory model or distributed memory model.
These all these dimensions would affect the portability of your application.
So when we work towards the end of the course, we will
have, will introduce emerging standards such as OpenCL and
Heterogeneous System Architecture, that will help
to address the portability of your applications.
So at this point, we have completed all the the
high-level introduction and complex information lectures.
So starting from next lecture we are going to be introducing the CUDA programming
interface and begin to to help you to develop your lab
application assignments. So for those of you who like to learn
more about the topic and the context information I would
like to encourage you to read chapter 1 of the textbook.
Thank you.